• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    NON-VOLATILE MEMORY WITH DIVIDED READ AND RECORD BIT LINES. The read and write operations of a non-volatile memory (NVM) bit cell have different optimal parameters, which results in a conflict during the design of the NVM bit cell. A single line of bits in the NVM bit cell prevents optimal read performance. Reading performance can be improved by dividing the reading path and the writing path in an NVM bit cell between two lines of bits. A line of read bits from the NVM bit cell has a low capacitance for improved read speed and decreased power consumption. A line of recording bits in the NVM bit cell has a low resistance to process large currents present during recording operations. The memory element of the NVM bit cell can be a fuse, an anti-fuse, an eFUSE or a magnetic tunnel junction. The reading performance can also be improved with reading operations with differential detection.
    公开号:BR112012033432B1
    申请号:R112012033432-8
    申请日:2011-06-28
    公开日:2020-11-10
    发明作者:Esin Terzioglu
    申请人:Qualcomm Incorporated；
    IPC主号:
    专利说明:

    Related Order Reference
    [0001] This application claims to benefit from US provisional patent application No. 61/359 155, entitled "Non-Volatile Memory with Split Write and Read Bitlines", filed on June 28, 2010. Field of the Invention
    [0002] The present description refers in general to a non-volatile memory (NVM). More specifically, the present description relates to improving the performance of non-volatile memory bit cells by dividing bit lines. Description of the State of the Art
    [0003] Non-volatile memory (NVM) bit cells, such as eFUSE bit cells, have a single line of bits for read and write operations for the bit cell and a single access transistor for read and write operations. recording. However, the read and write operations have different operational characteristics, which results in conflicts when designing the NVM bit cell. A conventional NVM bit cell will be described below with reference to Figure 1.
    [0004] Figure 1 is a circuit diagram illustrating a conventional non-volatile memory bit cell. An NVM bit cell 100 includes a fuse element 102 and an access transistor 104. Fuse element 102 is coupled to a bit line 112 and access transistor 104. A port on access transistor 104 is coupled to a word line 114.
    [0005] NUM bit cell write operations involve large currents better controlled by low resistance bit lines. In addition, the access transistor for a recording operation occupies a large chip area to handle large currents. Large, low-resistance bit lines have a large capacitance. For example, some conventional bit lines have capacitances of several picoFarads.
    [0006] Read operations on NUM bit cells involve small detection currents better controlled by low capacitance bit lines. Thus, a design conflict arises when an NVM bit cell is designed for read and write operations. The large capacitance of the bit lines for write operations results in low reading speeds and reading of medium and large surge currents. As a result of the sharing, by the NVM bit cell, of a single line of bits for read and write operations, the NVM bit cell cannot be designed for both high and low operating voltage. In addition, operation at multiple voltages (write voltage and read voltage) on a single bit line of the NVM bit cell increases the complexity of the peripheral circuitry coupled to the NVM bit cell.
    [0007] Alternative designs for NVM bit cells include a differential arrangement. Figure 2 is a circuit diagram illustrating a conventional non-volatile memory bit cell with differential detection. An NVM bit cell 200 includes a fuse element 202 coupled to an odd bit line 206 and a fuse element 222 coupled to an even bit line 226. An access transistor 204 is coupled to fuse element 202 and is controlled by an odd word line 214. An access transistor 224 is coupled to the fuse element 222 and is controlled by an even word line 234. Although the differential design can increase reading performance, the addition of a second line of bits increases the resistance of the bit lines because the layers of conductive lines (metal layers, for example) available in the insert are shared by the odd bit line 206 and the even bit line 226. When fewer layers of conductive lines are assigned to a bit line, the resistance of the bit line increases.
    [0008] There is therefore a need for a more secure and higher performance non-volatile memory bit cell. Summary of the Invention
    [0009] According to one embodiment, a cell of non-volatile memory (NVM) bits includes a first single recording NVM element coupled to a line of recording bits. The bit cell also includes a first recording access transistor that couples the first single earth record NVM element. A port on the first recording access transistor is coupled to a recording word line. The bit cell also includes a first read access transistor that couples the first single write NVM element to a line of read bits. A port on the first reading access transistor is coupled to a reading word line.
    [0010] According to another embodiment, a method of reading from a single recording non-volatile memory element (NVM) includes polarizing a line of recording bits coupled to the single recording NVM element to zero. The method also includes applying a high signal to a read word line to connect a read access transistor that couples the single write NVM element to a line of read bits. The method also includes detecting a current through the single write NVM element to determine the status of the single write NVM element.
    [0011] According to another embodiment, a method of recording on a single recording non-volatile memory (NVM) element includes applying a recording voltage to a line of recording bits coupled to the single recording NVM element. The method also includes applying a high signal to a recording word line to connect a recording access transistor, making current flow through the single recording NVM element.
    [0012] According to yet another modality, a device includes a non-volatile memory element (NVM) NVM of single recording. The apparatus also includes mechanisms for recording to the single-record NVM element coupled to the single-record NVM element. The device also includes a recording transistor that couples an NVM element with a single ground recording. A recording transistor port is coupled to a recording word line. The device also includes mechanisms for reading from the single-record NVM element. The device also includes a reading transistor that couples the single-record NVM element to the reading mechanism. A reading transistor port is coupled to a reading word line.
    [0013] This broadly describes the technical aspects and advantages of the present description so that the following detailed description can be better understood. Additional aspects and advantages of the description will be described below. Those skilled in the art should understand that this description can be readily used as a basis for modifying or designing other structures to achieve the same purposes as this description. Those skilled in the art should also realize that such equivalent constructions do not depart from the teachings of the description presented in the appended claims. The unpublished aspects, which are believed to be characteristics of the description, both as to their organization and method of operation, together with other objects and advantages, will be better understood with the following description, when considered in connection with the attached figures. It should be expressly understood, however, that each of the figures is presented for the purpose of illustration and description only and is not intended to be a definition of the limits of this description. Brief Description of Drawings
    [0014] For a more complete understanding of the present description, reference is now made to the following description, considered in conjunction with the attached drawings.
    [0015] Figure 1 is a circuit diagram illustrating a conventional non-volatile memory bit cell.
    [0016] Figure 2 is a circuit diagram illustrating a conventional non-volatile memory bit cell with differential detection.
    [0017] Figure 3 is a circuit diagram illustrating an exemplary non-volatile memory bit cell according to an embodiment.
    [0018] Figure 4 is a circuit diagram illustrating an exemplary non-volatile memory bit cell with differential detection according to a modality.
    [0019] Figure 5 is a circuit diagram illustrating an exemplary array of non-volatile memory bit cells according to a modality.
    [0020] Figure 6 is a circuit diagram illustrating an equivalent circuit for an exemplary non-volatile memory bit cell according to one embodiment.
    [0021] Figure 7 is a graph showing a bit cell resistance as a function of the bit cell height according to a modality.
    [0022] Figure 8 is a block diagram showing an exemplary wireless communication system in which a modality of the description can be advantageously used.
    [0023] Figure 9 is a block diagram that illustrates a design workstation used to design the circuit, layout and logic of a semiconductor component according to a modality. Detailed Description of the Invention
    [0024] Non-volatile memory (NVM) bit cells with separate physical bit lines for read and write operations offer improved read and write performance compared to NVM bit cells with a single bit line. Thus, a low line capacitance is displayed during read operations and a low resistance is displayed during write operations.
    [0025] Figure 3 is a circuit diagram illustrating an exemplary non-volatile memory bit cell according to an embodiment. An NVM bit cell 300 includes a memory element 302 coupled to a recording bit line 322. The memory element 302 can be, for example, a fuse, an anti-fuse, an eFUSE or a magnetic tunnel junction (MTJ ). According to one embodiment, the memory element 302 is a single recording device, which is recorded at most once per cell of bits. A recording access transistor 306 is coupled to memory element 302 and ground. A write access transistor port 306 is coupled to a write word line 316. A read access transistor 304 is coupled to memory element 302 and a read bit line 324. An access transistor port reading 304 is coupled to a reading word line 314.
    [0026] According to one embodiment, the reading bit line 324 is a low capacitance bit line for high performance reading operations. According to one embodiment, the recording bit line 322 is a low resistance bit line designed for high current recording operations. The resistance of the recording bit line 322 can be reduced by adding layers of metal to the recording bit line 322.
    [0027] A write operation can be performed on memory element 302 by isolating the reading bit line 324 and placing a low signal on the reading word line 314. A write voltage is applied to the reading bit line recording 322 and a high signal applied to recording word line 316. According to one embodiment, the recording voltage is 1.8 volts and the high signal is 1.0 volts. The recording access transistor 306 is connected to allow a current to flow through the memory element 302 from the recording bit line 322 to the ground coupled to the recording access transistor 306. According to one embodiment, the element of memory 302 is a fuse element and the current through memory element 302 breaks the fuse, which results in an open circuit in memory element 302 during read operations.
    [0028] A read operation can be performed on the memory element 302 by placing a low sign on the recording word line element 316. The recording bit line 322 is polarized to zero by a column protective element (not shown) and a high signal is applied to the reading word line 314. According to one embodiment, the high signal is 1.0 volts. Read access transistor 304 is connected to conduct current through memory element 302 from recording bit line 322 to reading bit line 324. The amount of current through memory element 302 can be measured to determining the status of memory element 302. For example, if memory element 302 is a fuse and no current passes through memory element 302, the memory element can be a "0". Alternatively, if the memory element 302 is a fuse and a current passes through the memory element 302, the memory element can be a "1". According to one embodiment, the current through the memory element 302 is detected by applying a voltage to the reading bit line 324. If the voltage of the reading bit line 324 rises significantly, the memory element 302 is a open circuit. If the voltage of the reading bit line 324 does not rise significantly, the memory element 302 is a short circuit.
    [0029] The exemplary NVM bit cell design of Figure 3 improves the reading performance by placing a low capacitance reading bit line 324 in the NVM 300 bit cell. The additional reading bit line 324 and the access transistor readout 304 occupies an additional insert area, however, the insert area occupied by the read access transistor 304 is significantly smaller than the insert area occupied by the write access transistor 306. Thus, the total insert area occupied by the exemplary NVM 300 bit cell design of Figure 3 is not significantly increased.
    [0030] According to another modality, a line of read bits is added to a differential NVM bit cell design. Figure 4 is a circuit diagram illustrating a cell of non-volatile memory bits with differential detection according to a modality. A differential NVM bit cell 400 includes a write bit line 430. The write bit line 430 is coupled to and shared by memory elements 402, 412. Memory element 402 is coupled to a read access transistor 404 and a write access transistor 406. Write access transistor 406 couples the memory element 402 to the ground and is controlled by a write word pair 410. The read access transistor 404 couples the write element memory 402 to a line of reading bits par 444 and is controlled by a line of reading words par 408.
    [0031] The memory element 412 is coupled to a write access transistor 416 and a read access transistor 414. The write access transistor 416 couples memory element 412 to the ground and is controlled by a line of odd write word 420. Read access transistor 414 couples memory element 412 to an odd read bit line 442 and is controlled by an odd read word line 418.
    [0032] During a read operation in the differential NVM bit cell, the current detected through memory element 412 can be compared with the current detected through memory element 402. For example, the operational amplifier (not shown) can compare the voltage present in the even reading bit line 444 and the odd reading bit line 442.
    [0033] The differential NVM bit cell 400 includes the single recording bit line 430, which has a low resistance. The resistance of the single recording bit line 430 is minimized or decreased by reducing the resources (metal lines, for example) shared between the recording bit line 430 and other recording bit lines (not shown). The read bit lines 442, 444 are designed so as to have a low capacitance to improve the reading operations without affecting the ability of the NVM 400 bit cell to process large current write operations.
    [0034] Figure 5 is a circuit diagram illustrating an exemplary array of non-volatile memory bit cells according to one embodiment. The array 500 includes several bit cells 570. Each bit cell, like bit cell 570, includes a memory element 502 coupled to a read access transistor 504 and a write access transistor 506. The element of memory 502 of bit cell 570 is coupled to a line of recording bits, WBL0. A port 516 of the write access transistor 506 is coupled to a write word line, WWL0, and a port 514 of the read access transistor 504 is coupled to a read word line RWL0. Read access transistor 504 couples memory element 502 to a line of read bits, RBL0. The recording access transistor 506 couples the memory element 502 to a source line, SL0, which can be coupled to the ground, for example.
    [0035] Bit cell 570 is repeated along columns 550, 552, 554 which correspond to bit lines RBL0 and WBL0, RBL1 and WBL1 and RBLn and WBLn. Although only three columns are shown in the 500 array, additional columns may be present. Bit cell 570 is also repeated along rows 560, 562, 564, 566 which correspond to word lines RWL0 and WWL0, RWL1 and WWL1, RWL2 and WWL2, and RWLn and WWLn. Although only four rows are shown in arrangement 500, additional rows may be present.
    [0036] Non-volatile memory (NVM) bit cells with separate read and write paths allow for better performance of reading operations, energy consumption in lower reading operations and higher speed of reading operations. In addition, separating the path of low voltage reading operations from the path of high voltage recording operations significantly reduces the complexity of the peripheral circuits, resulting in a reduction in the chip area consumed by the peripheral circuits.
    [0037] The performance of NVM bit cells can also be improved by minimizing or reducing resistance by selecting a non-square bit cell geometry. Figure 6 is a circuit diagram illustrating a circuit equivalent to an exemplary NVM bit cell according to an embodiment. Resistor 602 represents a parasitic resistance at the chip level, resistance 606 represents a bit line resistance and resistance 612 represents a source parasitic resistance. Transistor 604 represents a column selection transistor and transistor 610 represents a program transistor. A memory element 608 is coupled between the bit line resistor 606 and the program transistor 610.
    [0038] When selecting a bit cell geometry, a compensation occurs between the height of the bit cell and the width of the bit cell. A higher bit cell results in a lower program transistor resistance 610, but a higher bit line resistance 606. For a given bit cell width, an effective resistance of bit line resistance 606 and program transistor resistance 610 is given by: Reff = n * Rm * y + RdS / (f * y), where n is the number of rows per line of bits, Rm is the resistance of the line of bits per unit height, y is the height of the cell of bits, Ris is the linear resistance of the program transistor and f is the number of layout fingers inside the bit cell layout.
    [0039] Figure 7 is a graph that illustrates the resistance of a bit cell as a function of the height of the bit cell according to a modality. Graph 700 shows in line 702 the effective resistance as a function of the height of the bit cell. Graph 700 also illustrates, in line 704, the size of the bit cell as a function of the height of the bit cell. Graph 700 demonstrates that the minimum resistance is not always obtained at a minimum height of the cell.
    [0040] Figure 8 is a block diagram showing an exemplary wireless communication system 800 in which a modality of the description can be used advantageously. For illustration purposes, Figure 8 shows three remote units 820, 830 and 850 and two base stations 840. It will be recognized that wireless communication systems can have many more remote units and base stations. Remote units 820, 830 and 850 include IC devices 825A, 825C and 825B, which include the described non-volatile memory. It will be recognized that any device that contains an IC can also include the non-volatile memory bit cell described herein, including base stations, switching devices and network equipment. Figure 8 shows forward link signals 880 from base station 840 to remote units 820, 830 and 850 and reverse link signals 890 from remote units 820, 830 and 850 to base stations 840.
    [0041] In Figure 8, remote unit 820 is shown as a mobile phone, remote unit 830 is shown as a handheld computer and remote unit 850 is shown as a fixed location remote unit in a local wireless circuit system . For example, remote units can be mobile phones, portable personal communication systems (PCS) units, portable data units such as personal data assistants, GPS enabled devices, navigation devices, converters, music players, video playback apparatus, entertainment units, fixed location data units such as meter reading equipment or any other device that stores or retrieves data or computer instructions or any combination thereof. Although Figure 8 illustrates remote units in accordance with the teachings of the description, the description is not limited to these exemplary units shown. The description modalities can be used appropriately in any device that includes a memory device.
    [0042] Figure 9 is a block diagram that illustrates a design workstation used to design the circuit, layout and logic of a semiconductor component, such as a cell of non-volatile memory bits described above. A 900 designed workstation includes a 901 hard drive that contains operating system software, support files and designed software such as Cadence or OrCAD. The design workstation 900 also includes a monitor to facilitate the design of a 910 circuit or semiconductor component 912, such as a non-volatile memory. A storage medium 904 is provided to tangibly store circuit design 910 or semiconductor component 912 can be stored on storage medium 904 in a file format such as GDSII or GERBER. The storage medium 904 can be a CD-ROM, a DVD, a hard disk, a flash memory or other suitable device. In addition, the design workstation 900 includes a drive device 903 for receiving input from or recording output to storage medium 904.
    [0043] The data recorded on the storage medium 904 can specify logic circuit configurations, pattern data for photolithography masks or mask pattern data for serial recording tools, such as electron beam lithography. The data can also include logical verification data, such as timing diagrams or network circuits associated with logical simulations. Providing data on the storage medium 904 facilitates the design of the 910 circuit design or semiconductor component 912 by decreasing the number of processes for designing semiconductor boards.
    [0044] For an implementation in firmware and / or software, the methodologies can be implemented with modules (for example, procedures, functions and so on) that perform the functions described here. Any machine-readable medium, which tangibly incorporates instructions, can be used in the implementation of the methodologies described here. For example, software codes can be stored in memory and executed by a processor unit. The memory can be implemented inside the processor unit or external to the processor unit. As used herein, the term "memory" refers to any type of long-term, short-term or other memory and should not be limited to any specific type of memory or number of memories, or the type of media on which memory is stored.
    [0045] If implemented in firmware and / or software, the functions can be stored as one or more instructions or code in a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media includes storage media on physical computers. A storage medium can be any available medium that can be accessed by a computer. By way of example, and not by way of limitation, such computer-readable media may comprise RAM, ROM, EEPROM, CD-ROM or any other optical disk storage, magnetic disk storage or other magnetic storage devices or any other means that may be used to carry or store desired program code in the form of instructions or data structures and which can be accessed by a computer; the term disc (disk and disc), as used here, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disc and blu-ray disc, in which usually discs (disks) reproduce magnetically, while discs reproduce data optically with lasers. Combinations of them should also be included within the scope of computer-readable media.
    [0046] In addition to storage in a computer-readable medium, instructions and / or data can be provided as signals on transmission media included in a communication device. For example, a communication device may include a transceiver that has signals that indicate instructions and data. Instructions and data can be configured to have one or more processors implement the functions outlined in the claims.
    [0047] Although a specific circuit set has been shown, those skilled in the art will understand that not all of the described circuit set is necessary to put the description into practice. Furthermore, certain notoriously known circuits have not been described, in order to keep the focus on the description. Similarly, although the description refers to a logical "0" and a logical "1" in certain places, those skilled in the art understand that the logic values can be switched, with the rest of the circuit being adjusted accordingly, without affect the operation of the present invention.
    [0048] Although the present description and its advantages have been described in detail, it should be understood that several changes, substitutions and modifications can be made without abandoning the technology of the description defined by the attached claims. For example, relational terms, such as "above" and "below", are used with respect to a substrate or electronic device. Evidently, if the substrate or electronic device is inverted, above it becomes below and vice versa. In addition, if oriented to the sides, above and below they can refer to the sides of a substrate or electronic device. Furthermore, the scope of this application is not intended to be limited to the specific modalities of the process, machine, fabrication, material composition, mechanisms, methods and steps described in the report. As those skilled in the art will readily understand from the description, the processes, machines, manufacturing, compositions of matter, mechanisms, methods or steps, currently existing or to be further developed, that perform substantially the same function or achieve substantially the same result as corresponding modalities described herein can be used in accordance with the present description. Accordingly, the appended claims are intended to include, within the scope of such processes, machines, manufacturing, compositions of matter, mechanisms, methods or steps.
    权利要求:
    Claims (14)
    [0001]
    1. Non-volatile memory bit cell, NVM (300, 400, 570), comprising: a first element (302, 402, 412, 502) single write NVM directly coupled to a line of write bits (322, 430, WBL0); a first transistor (306, 406, 506) for recording access that couples the first element (302, 402, 412, 502) NVM for single recording to ground, a port for the first transistor (306, 406, 506) for access to the recording coupled to a recording word line (316, 410, 420, WWL0); and a first read access transistor (304, 404, 414, 504) directly coupled to the first element (302, 402, 412, 502) NVM of single write and directly coupled to a line of reading bits (324, 442, 444, RBL0), a port of the first read access transistor (304, 404, 414, 504) coupled to a read word line (314, 408, 418, RWL0); the NVM bit cell being characterized by the fact that: a second element (302, 402, 412, 502) single recording NVM coupled to the recording bit line (322, 430, WBL0); a second transistor (306, 406, 506) for recording access that couples the second element (302, 402, 412, 502) NVM for single recording to ground, a port for the second transistor (306, 406, 506) for access to the recording coupled to a word line (316, 410, 420, WWL0) of odd recording; and a second read access transistor (304, 404, 414, 504) that couples the second NVM single recording element (302, 402, 412, 502) to a line of bits (324, 442, 444, RBL0) of odd reading, a door of the second transistor (304, 404, 414, 504) for reading access coupled to an odd reading word line (314, 408, 418, RWL0), in which the first element (302, 402, 412, 502) Single write NVM is coupled to an even reading bit line (324, 442, 444, RBLO) and the first transistor port (304, 404, 414, 504) to read access is coupled to a even reading word line (314, 408, 418, RWL0).
    [0002]
    2. Bit cell (300, 400, 570), according to claim 1, characterized by the fact that the elements (302, 402, 412, 502) NVM of single recording are at least one among a fuse, an anti -fuse, an eFUSE and a magnetic tunnel junction, MTJ.
    [0003]
    3. Bit cell (300, 400, 570), according to claim 1, characterized by the fact that the reading bit line (324, 442, 444, RBLO) is a low capacitance line and the reading line recording bits (322, 430, WBLO) is a low resistance line.
    [0004]
    4. Bit cell (300, 400, 570) according to claim 1, characterized in that the bit cell (300, 400, 570) occupies a non-square chip area.
    [0005]
    5. Bit cell (300, 400, 570) according to claim 1, characterized by the fact that the bit cell (300, 400, 570) is integrated into a memory array.
    [0006]
    6. Bit cell (300, 400, 570), according to claim 5, characterized by the fact that the memory arrangement is integrated with a mobile phone, a set top box, a music player, a device video playback, an entertainment unit, a navigation device, a computer, a personal wireless communication systems unit, PCS, laptop, a portable data unit and / or a fixed location data unit.
    [0007]
    Apparatus characterized by the fact that it comprises the bit cell as defined in any one of claims 1, 2, 5 or 6.
    [0008]
    Apparatus according to claim 7, characterized by the fact that it additionally comprises a column storer adapted to polarize the line of bits (322, 430, WBLO) of recording to zero during a reading operation.
    [0009]
    9. Method of reading element (302, 402, 412, 502) of a single write of non-volatile memory, NVM, of a bit cell as defined in any one of claims 1 to 6, the method characterized by the fact that comprises: polarizing a line of recording bits (322, 430, WBLO) directly coupled to at least one element (302, 402, 412, 502) single recording NVM selected to zero; apply a high signal to a reading word line (314, 408, 418, RWL0) to connect a read access transistor (304, 404, 414, 504) directly coupled to the element (302, 402, 412, 502) Single write NVM selected and directly coupled to the read bit line (324, 442, 444, RLB0); place a low signal on a read word line (316, 410, 420, WWL0) of the write access transistor (306, 406, 506) coupled to the selected single write NVM element (302, 402, 412, 502) ; and detecting a current through the single recording element (302, 402, 412, 502) selected to determine a state of the single recording element (302, 402, 412, 502).
    [0010]
    10. Method according to claim 9, characterized by the fact that the polarization of the recording bit line (322, 430, WBLO) is carried out by a column maintenance element.
    [0011]
    11. Method according to claim 10, characterized in that it additionally comprises comparing the current detected through the element (302, 402, 412, 502) NVM of single recording with a second current detected through an element (302, 402, 412, 502) Different single write NVM.
    [0012]
    12. Method, according to claim 10, characterized by the fact that it additionally comprises the element (302, 402, 412, 502) NVM of single recording in a mobile phone, a set top box, a music playback device , a video player, an entertainment unit, a navigation device, a computer, a wireless personal communication systems unit, PCS, laptop, a portable data unit and / or a fixed location data unit .
    [0013]
    13. Method of recording in a single recording element (302, 402, 412, 502) of non-volatile memory, NVM of a bit cell, the method characterized by the fact that it comprises: isolating the bit line (324, 442, 444, RBLO) of reading directly coupled to the transistor (304, 404, 414, 504) of access to the reading; apply a low signal to a reading word line (314, 408, 418, RWLO) to turn off the read access transistor (304, 404, 414, 504) directly coupled to an element (302, 402, 412, 502 ) Single recording NVM selected; applying a recording voltage to a recording bit line (322, 430, WBLO) coupled to at least one selected recording element (302, 402, 412, 502); and applying a high signal to a recording word line (316, 410, 420, WWL0) to connect the recording access transistor (306, 406, 506) directly coupled to an element (302, 402, 412, 502) Single write NVM selected, causing a current to flow through the selected element (302, 402, 412, 502) Single write NVM.
    [0014]
    14. Method according to claim 13, characterized by the fact that it additionally comprises integrating the element (302, 402, 412, 502) NVM of single recording in a mobile phone, a set top box, a music playback device , a video player, an entertainment unit, a navigation device, a computer, a portable personal wireless communication systems (PCS) unit, a portable data unit and / or a fixed location data unit .
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    法律状态:
    2018-12-26| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|
    2020-06-09| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|
    2020-11-10| B16A| Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 28/06/2011, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    US35915510P| true| 2010-06-28|2010-06-28|
    US61/359,155|2010-06-28|
    US12/849,862|US8331126B2|2010-06-28|2010-08-04|Non-volatile memory with split write and read bitlines|
    US12/849,862|2010-08-04|
    PCT/US2011/042092|WO2012003165A1|2010-06-28|2011-06-28|Non-volatile memory with split write and read bitlines|
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